Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to nonvolatile memory devices capable of adjusting a maximum verify time of a program loop according to a page address.
Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM), and examples of nonvolatile memory devices include flash memory, electrically erasable programmable read-only memory (EEPROM), and resistive random access memory (RRAM).
A flash memory device comprises a plurality of memory cells arranged in a memory cell array. The memory cell array is organized in a plurality of memory blocks, with each of the memory blocks comprising a plurality of pages. Each of the plurality of pages comprises a plurality of memory cells. The flash memory device typically performs erase operations on a block-by-block basis, and it performs program operations and read operations on a page-by-page basis.
Each of the plurality of memory cells can be identified as an on-cell or an off-cell according to whether it turns on in response to a predetermined voltage. In other words, the memory cells can be identified as on-cells and off-cells according to their respective threshold voltages. For example, where a memory cell is in an erased state, it may be an on-cell when a voltage of 0V is applied to its control gate. On the other hand, where a memory cell is in a programmed state, it may be an off-cell when the voltage of 0V is applied to its control gate.
In a NAND flash memory device, memory cells are arranged in a cell string structure, where each cell string comprises a plurality of transistors connected in series between a string selection transistor connected to a string selection line (SSL) and a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to a bit line and the ground selection transistor is connected to a common source line (CSL).
Each of a plurality of memory cells can be a single level cell (SLC), which is a memory cell that stores one bit, or a multi level cell (MLC), which is a memory cell that stores more than one bit. An SLC has an erase state and a program state, and an MLC has an erase state and a plurality of program states.
To accurately read stored data, a flash memory device must be able to reliably distinguish between different program states. For this to happen, there must be adequate read margins between threshold voltage distributions corresponding to these program states. Unfortunately, however, these read margins can be diminished by noise that causes the threshold voltage distributions to widen, such as CSL noise.
CSL noise is an undesired change in a voltage of the CSL. CSL noise can alter the amount of current flowing through an on-cell during a read operation or a program operation, which can increase the threshold voltage of the on-cell. For example, even with an identical word line voltage or an identical bit line voltage, the current flowing through the on-cell decreases when a voltage level of a source node of a ground selection transistor increases due to CSL noise. This causes a threshold voltage of the on-cell to increase so it is misinterpreted as an off-cell. This can cause an error in the read or program operation.